How to put a list of cells into a submodule in yosys -

i trying write procedure put each connected component of given circuit distinct sub-module.

so, tried add function scc pass in yosys add each scc submod. function is:

  void putselectionintoparition (rtlil::design *design,                   std::vector<pair<std::string,rtlil::selection>>& selectionvector)   {     int p_count = 0;     (std::vector<pair<std::string,rtlil::selection>>::iterator = selectionvector.begin();      != selectionvector.end(); ++it)        {     design->selection_stack[0] = it->second;     design->selection_stack[0].optimize(design);     std::string command = "submod -name ";     command.append(it->first);     pass::call_on_selection(design, it->second, command);      ++p_count;     }    } 

however, code not work properly. guess problem "selection" process use. wondering if there utility/api inside yosys source accept vector of cells (as , name submodule) , put them sub-module.

the following should work fine:

void putselectionintoparition(rtlil::design *design,     std::vector<pair<std::string, rtlil::selection>> &selectionvector) {     (auto : selectionvector) {         std::string command = "submod -name " + it.first;         pass::call_on_selection(design, it.second, command);     } } 

you don't need (nor should) modify selection_stack.

i wondering if there utility/api inside yosys source accept vector of cells (as , name submodule) , put them sub-module.

you setting submod="<name>" attribute on cells. run submod command.

you might have seen scc documentation mentions -set_attr option yet unimplemented. have implemented option in commit ef603c6 (commit 914aa8a contains bugfix scc).

with feature can accomplished have described using following yosys script.

read_verilog test.v prep scc -set_attr submod scc{} submod show test 

i have tested folling test.v file:

module test(input a, b, output x, y); assign x = (a & b) ^ x, y = | (b ^ y); endmodule 

3. executing scc pass (detecting logic loops). found scc: $xor$test.v:2$2 found scc: $or$test.v:2$4 $xor$test.v:2$3 found 2 sccs in module test. found 2 sccs.